277M Signal Delay Unit

The modern clone 277 modules are built using digital signal processors. The 277, designed in 1972, was likely one of the first digital delay units. It uses 48 256 bit shift registers to provide a delay from 50 mS to 200 mS.


The design is two PCBs with front panel wiring.


The schematics for the 277 are in very poor condition and portions are literally unreadable. They also contain errors. In bringing up this module I had to make some assumptions and modify portions of the circuitry for correct functionality. Only one prototype and three modules were ever built.

277 Documentation


The shift registers are single bit so the incoming signal is simply digitized at the zero crossing. This is then synchronized with the bit clock for the shift register data input. The shift registers are Intel 1404. The original modules used can packages while this version uses DIP.

The VCO is complex and strange. It is a fixed-slope integrator so the frequency adjustment changes the amplitude of the triangle. As such there is an upper and lower limit. The shift register depth is 12,288 bits so the delay time corresponds to a frequency range of 245,760 Hz to 61,440 Hz. The VCO operation is limited to about 60 KHz to 320 KHz. I tweaked some resistor values to center the frequency over this range. A diode in the CV sum op-amp limits negative voltages and the upper limit is just over 8V. I changed this diode to a 9.1V zener to limit the upper and lower frequencies so the VCO wouldn't stop. As such, on the maximum delay the CV will only decrease the delay. Conversely, on the minimum delay the CV will only increase the delay.

The shift registers operate from +/-5V or +5/-9V. The schematic shows the shift registers operating from 0/-10V but there is no -10V regulator in the schematics. In addition, the termination resistors used correspond to 10V operation. Rather than run the shift registers at 0/-15V I added a LM337 to for -10V operation with the existing termination resistors. I also changed the DS00025 clock driver to operate at -10V. I'm not sure why Don chose to operate the shift registers at -10V. It made the data recovery a bit easier but complicated the shift data circuitry.

-24V was used for the clock driver circuitry. This minimizes high frequency noise on the -15V and also supplies the headroom necessary if the shift registers operated on 0/-15V. A DC-DC converter to generate the-24V added enough noise that the input mixer and comparator were unstable. I needed a quieter -24V solution but since the shift registers are operating on -10V, -15V could be used for the driver. I added a RC network and powered the clock drivers from -15V. This added a minimal amount of high frequency noise to the -15V.

The circuitry to level shift the data has obvious errors and did not function. I redesigned this circuitry for proper waveforms. In addition, the schematics show this synchronized data being fed back to the input of the comparator. I could see no reason for this. The levels are negative and the comparator is setup for zero-crossing detection so it just messed everything up. I eliminated this feedback and added hysteresis to the comparator to eliminate jitter at the zero crossing.

I'm not sure all these changes are "authentic" but lacking error-free readable schematics these changes were necessary for functional operation.

PCB1 contains all of the circuitry except the shift registers and clock driver. The LM337 -10V regulator is added in the extra space and the small blue wire and missing components are part of my shift register data modification. The added hysteresis resistor is on the rear.


PCB2 contains the 48 shift registers and clock drivers. The -15V RC filter is the tantalum capacitor and resistor.




The module operates fairly well given that the analog signal is digitized to a single bit. As such the output signal is always full amplitude. Different delay outputs can be fed back to create echoes but careful adjustment of the mixer is required to prevent the 277 from self-oscillating at low frequencies.